1. Field of the Invention
This disclosure relates generally to memory systems, and more specifically, to pipelined memory systems.
2. Description of the Related Art
In general, a memory circuit is designed to meet a particular performance target at a particular operating point. Performance targets may be defined by latency and power consumption of the memory circuit at a peak performance operating point, e.g., peak control clock signal frequency and a particular power supply voltage. To achieve the performance target, the memory circuit may be pipeline-accessed with state elements (e.g., latch circuits, flip-flops, or other suitable state elements) inserted between logic circuits. Typically, individual pipeline stages of a pipelined memory circuit are designed to utilize the entire period of the control clock signal at the operating point associated with the performance target. However, the propagation delay through an individual pipeline stage of the pipelined memory circuit, i.e., the delay from the input of the individual pipeline stage to the output of the individual pipeline stage, is not constant in real operating conditions. The propagation delay may change due to variations in temperature, power supply voltage, or other operating conditions.
The use of the same reference symbols in different drawings indicates similar or identical items.